Complementary metal oxide semiconductor (CMOS) circuits are formed by N-type and P-type MOS transistors and generally dissipate less power. Thus, CMOS circuits are often used to form semiconductor devices. When a power supply having a high potential VDD and a low potential VSS is used, a CMOS circuit can output a binary pulse signal exhibiting the high and low potentials VDD and VSS. Namely, a CMOS circuit can be configured so that P- and N-type MOS transistors output high and low potentials, respectively, when these transistors are brought in a conductive state. However, since P- and N-type MOS transistors need to be formed to manufacture a CMOS device, an impurity implantation process needs to be carried out a plurality of times, in addition to processes such as for film formation, mask exposure, and etching. Thus, manufacturing costs are increased.
In contrast, to manufacture a semiconductor device formed only by MOS transistors of a single conductivity type (either P- or N-type MOS transistors), a smaller number of impurity implantation processes and the like is required. Thus, for this type of semiconductor devices, manufacturing costs are less than those of CMOS devices. However, because of a single conductive property, these semiconductor devices dissipate more power and have a narrower output margin, compared with CMOS devices. For example, if a circuit is formed only by P-type MOS transistors, when outputting a low voltage, the circuit outputs a voltage higher than the low potential VSS by a threshold voltage of the transistors. If a circuit is formed only by N-type MOS transistors, when outputting a high voltage, the circuit outputs a voltage lower than the high potential VDD by a threshold voltage of the transistors.
In order to obtain an increase in amplitude, dynamic circuits using a bootstrap effect have been proposed and used. FIG. 18 illustrates an example of a conventional bootstrap circuit based on Patent Document 1. This bootstrap circuit includes: an N-type MOS transistor 101 connecting a power supply VDD and an output terminal Out; an N-type MOS transistor 102 inputting an input pulse signal In to a gate electrode (node N1) of the transistor 101; a coupling capacitor 103 connecting a source electrode and the gate electrode of the transistor 101; and an N-type MOS transistor 104 connecting a power supply VSS and the output terminal Out. A gate electrode of the transistor 102 is connected to the power supply VDD, and a gate electrode of the transistor 104 is supplied with an input pulse signal Inb. The input pulse signal In is increased to VDD at a high level and decreased to VSS at a low level, and the input pulse signal Inb is an inverted signal of the input pulse signal In.
FIG. 19 is a timing diagram of an operation of the above bootstrap circuit. First, in a period t2, the pulse signals Inb and In are brought to high and low potentials VDD and VSS, respectively. Since the transistors 102 and 104 are brought in a conductive state, potentials at the node N1 and the output terminal Out are decreased to the low potential VSS. Next, in a period t3, the pulse signal Inb is decreased to the low potential VSS, and the pulse signal In is increased to the high potential VDD. Accordingly, the transistor 104 is brought in a non-conductive state. In addition, the potential at the node N1 begins to increase from the low potential VSS via the transistor 102. When the potential at the node N1 reaches VDD−Vth (Vth is a threshold voltage of the transistor 102), the transistor 102 is brought in a non-conductive state. Thus, the potential at the node N1 does not exceed the potential VDD−Vth. Assuming that the low potential VSS at the output terminal Out is a source voltage and the potential VDD−Vth at the node N1 is a gate voltage, if the gate-source voltage is above a threshold voltage of the transistor 101, the transistor 101 is brought in a conductive state. Namely, the potential at the output terminal Out is increased toward the high potential VDD via the transistor 101, and the potential at the node N1 connected to the coupling capacitor 103 is also increased. Since both the gate and source potentials of the transistor 102 are brought to VDD, the transistor 102 is brought in a non-conductive state. Thus, the transistor 102 does not prevent the increase of the potential at the node N1. As a result, the potential at the node N1 exceeds the high potential VDD, and the potential at the output terminal Out is increased to the high potential VDD. The threshold voltage Vth is defined as a gate-source voltage necessary to cause an effective amount of current flow between a source and a drain (10−7 ampere, for example).
Further, Patent Document 2 discloses a method for increasing a potential at a node for which a bootstrap effect is produced to VDD, without being decreased to VDD−Vth. FIG. 20 illustrates a circuit including: transistors 111 and 113 connected to an output terminal Vw; a transistor 112 supplying an input signal S to a gate of the transistor 111; an inverter 115 inverting the signal S; a delay circuit 116 delaying the inverted signal outputted from the inverter 115 and supplying the delayed signal to a gate of the transistor 113 and a drain of a transistor 114, that is, to a node N3; and the transistor 114 connecting a gate of transistor 112 and the node N3. Based on this circuit, in order to increase a potential at a node N2 for which a bootstrap effect is produced to VDD independent of a threshold voltage of the transistor 112, a potential at a node N6 is increased to exceed VDD by another bootstrap effect. FIG. 21 is a timing diagram of an operation of the circuit of FIG. 20.
Furthermore, Patent Document 3 discloses a voltage generation circuit for increasing a potential at a node for which a bootstrap effect is produced to VDD, without being decreased to VDD−Vth. The voltage generation circuit of FIG. 22 corresponds to a circuit connected to the gate of the transistor 102 in FIG. 18. When signals ω0 and ω1 are at a high potential VDD, potentials at nodes N21 and N23 are brought to a low potential VSS and to VDD−Vth, respectively, to charge a capacitor C1. When the potential at the node N21 is inverted to the high potential VDD, the potential at the node N23 is increased to VDD−Vth+VDD−VSS, to bring a transistor T11 in a conductive state and charge an output G close to VDD. Further, when the potential at the node N21 is inverted to the low potential VSS, since a potential at a node N22 is increased toward VDD, the output G is increased above VDD.    Patent Document 1: Japanese Patent Kokai Publication No. JP-P2004-64528A    Patent Document 2: Japanese Patent Kokai Publication No. JP-A-11-39865    Patent Document 3: Japanese Patent Kokai Publication No. JP-A-1-94591